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SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 1 post office box 655303 ? dallas, texas 75265 compatible with ieee std 1194.1-1991 (btl) ttl a port, backplane transceiver logic (btl) b port open-collector b -port outputs sink 100 ma bias v cc minimizes signal distortion during live insertion or withdrawal high-impedance state during power up and power down b -port biasing network preconditions the connector and pc trace to the btl high-level voltage ttl-input structures incorporate active clamping to aid in line termination package options include high-power shrink quad flat (pca) package with 0.5-mm pin pitch and ceramic quad flat (hqa) package bg v nc v cc gnd 1ao6 1ai6 1ao7 1ai7 gnd 1ao8 1ai8 1ao9 1ai9 gnd 2clk nc 2ao2 2ai2 gnd 2ao3 2ai3 2ao4 2ai4 gnd v cc nc SN54FB1651 . . . hqa package sn74fb1651 . . . pca package (top view) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1b2 gnd 1b3 1b4 gnd 1b5 1b6 gnd 1b7 1b8 gnd 1b9 nc 2clkab gnd 2b2 2b3 gnd 2b4 2b5 gnd 2b6 2b7 gnd 2b8 gnd 2ao6 gnd 2ao7 2ao8 v v cc 2ai7 2clkab 2oea 2leab gnd 2ao9 gnd 1oeb 1oea 1leab 2oeb 2oeb 2leba 2clkba 1clkab 2ai8 gnd 1ao1 gnd 2ai9 cc 2oea 2ai6 cc 1oeb 1leba 1clkba 1oea 1ai1 1ao2 1ai2 1ao3 1ai3 1ao4 1ai4 1ao5 1ai5 2ao5 2ai5 nc no internal connection 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1b1 bg gnd nc 2b9 cc bias v copyright ? 1997, texas instruments incorporated unless otherwise noted this document contains production data information current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. on products compliant to mil-prf-38535, all parameters are tested unless otherwise noted. on all other products, production processing does not necessarily include testing of all parameters.
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 2 post office box 655303 ? dallas, texas 75265 description the 'fb1651 contain an 8-bit and a 9-bit transceiver with a buffered clock. the clock and the transceivers are designed to translate signals between ttl and backplane transceiver logic (btl) environments. they are specifically designed to be compatible with ieee std 1194.1-1991. the b port operates at btl-signal levels. the open-collector b ports are specified to sink 100 ma. two output enables (oeb and oeb ) are provided for the b outputs. when oeb is low, oeb is high, or v cc is less than 2.1 v, the b port is turned off. the a port operates at ttl-signal levels. the a outputs reflect the inverse of the data at the b port when the a-port output enable (oea) is high. when oea is low or when v cc is less than 2.1 v, the a outputs are in the high-impedance state. bias v cc establishes a voltage between 1.62 v and 2.1 v on the btl outputs when v cc is not connected. bg v cc and bg gnd are the supply inputs for the bias generator. the SN54FB1651 is characterized for operation over the full military temperature range of 55 c to 125 c. the sn74fb1651 is characterized for operation from 0 c to 70 c. function tables transceiver inputs function oea oea oeb oeb function x x h l a data to b bus l h x x b data to a bus l h h l a data to b bus, b data to a bus x x l x b-bus isolation x xxh b - b us i so l a ti on h x x x a-bus isolation x l x x a - b us i so l a ti on storage mode inputs function le clk function h x transparent l store data l l storage
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 3 post office box 655303 ? dallas, texas 75265 functional block diagram to eight other channels 1d c2 c1 1d c2 c1 1oeb 1oeb 1clkab 1leab 1leba 1clkba 1oea 1oea 1ai1 1ao1 1b1 81 80 83 82 85 84 87 86 90 89 76 transceiver
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 4 post office box 655303 ? dallas, texas 75265 functional block diagram (continued) to seven other channels 2oeb 2oeb 2clkab 2leab 2leba 2clkba 2oea 2oea 2clkab 1d c2 c1 1d c2 c1 2b2 2ai2 2ao2 2clk delay delay 45 46 43 44 41 42 39 40 14 17 16 62 60 transceiver
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 5 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc , bias v cc , bg v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : except b port 1.2 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b port 1.2 v to 3.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any b output in the disabled or power-off state, v o 0.5 v to 3.5 v . . . . . . . . . . . . . . voltage range applied to any output in the high state, v o 0.5 v to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik : except b port 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b port 18 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current applied to any single output in the low state, i o : a port 48 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b port 200 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 1): pca package 33 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions (see note 2) SN54FB1651 sn74fb1651 unit min nom max min nom max unit v cc, bg v cc , bias v cc supply voltage 4.5 5 5.5 4.5 5 5.5 v v ih high-level input voltage b port 1.62 2.3 1.62 2.3 v v ih hi g h - l eve l i npu t vo lt age except b port 2 2 v v il low-level input voltage b port 0.75 1.47 0.75 1.47 v v il l ow- l eve l i npu t vo lt age except b port 0.8 0.8 v i ik input clamp current 18 18 ma i oh high-level output current a port 3 3 ma i ol low-level output current a port 24 24 ma i ol l ow- l eve l ou t pu t curren t b port 100 100 m a t a operating free-air temperature 55 125 0 70 c note 2: unused pins (input or i/o) must be held high or low to prevent them from floating. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 6 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range parameter test conditions SN54FB1651 sn74fb1651 unit parameter test conditions min typ 2 max min typ 2 max unit v ik b port v cc = 4.5 v, i i = 18 ma 1.2 1.2 v v ik except b port v cc = 4.5 v, i i = 40 ma 0.5 0.5 v v oh ao port v cc =45v i oh = 1 ma v v oh ao por t v cc = 4 . 5 v i oh = 3 ma 2.5 3.3 2.5 3.3 v v ao port v cc = 4.5 v, i ol = 24 ma 0.35 0.5 0.35 0.5 v v ol b port v cc =45v i ol = 80 ma 0.75 1.1 0.75 1.1 v ol b port v cc = 4 . 5 v i ol = 100 ma 1.15 1.15 i i except b port v cc = 5.5 v, v i = 5.5 v 50 50 m a i ih 3 except b port v cc = 5.5 v, v i = 2.7 v 50 50 m a i il 3 except b port v cc = 5.5 v, v i = 0.5 v 50 50 m a i il 3 b port v cc = 5.5 v, v i = 0.75 v 100 100 m a i ozh ao port v cc = 5.5 v, v o = 2.7 v 50 50 m a i ozl ao port v cc = 5.5 v, v o = 0.5 v 50 50 m a i ozpu ao port v cc = 0 to 2.1 v, v o = 0.5 v to 2.7 v 50 50 m a i ozpd ao port v cc = 2.1 v to 0, v o = 0.5 v to 2.7 v 50 50 m a i oh b port v cc = 0 to 5.5 v, v o = 2.1 v 100 100 m a i os ? a port v cc = 5.5 v, v o = 0 30 150 30 150 ma i cc a port to b port v cc =55v i o =0 100 100 ma i cc b port to a port v cc = 5 . 5 v , i o = 0 120 120 m a c i ai port v i =05vor25v 5.5 5.5 pf c i control inputs v i = 0 . 5 v or 2 . 5 v 5.5 5.5 p f c o ao ports v o = 0.5 v or 2.5 v 5.5 5.5 pf c io b port per ieee std 1194.1-1991 v cc = 0 to 5.5 v 5.5 5.5 pf 2 all typical values are at v cc = 5 v, t a = 25 c. 3 for i/o ports, the parameters i ih and i il include the off-state output current. this parameter is warranted but not production tested. ? not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. live-insertion specifications over recommended operating free-air temperature range parameter test conditions SN54FB1651 sn74fb1651 unit parameter test conditions min max min max unit i cc (bias v cc ) v cc = 0 to 4.5 v v b =0to2v v i (bias v cc )=45vto55v 450 450 m a i cc (bias v cc ) v cc = 4.5 v to 5.5 v v b = 0 t o 2 v , v i (bias v cc ) = 4 . 5 v t o 5 . 5 v 10 10 m a v o b port v cc = 0, v i (bias v cc ) = 5 v 1.62 2.1 1.62 2.1 v i v cc = 0 , v b = 1 v, v i (bias v cc ) = 4.5 v to 5.5 v 1 1 a i o b port v cc = 0 to 5.5 v, oeb = 0 to 0.8 v 100 100 m a o p v cc = 0 to 2.2 v, oeb = 0 to 5 v 100 100 m product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 7 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) v cc =5v SN54FB1651 sn74fb1651 unit v cc = 5 v , t a = 25 c SN54FB1651 t a = 0 c to 70 c t a = 40 c to 85 c unit min max min max min max min 2 max 2 f clock clock frequency 0 150 0 150 0 150 0 150 mhz t w pulse duration, clk or le 3.3 3.3 3.3 3.3 ns t su setup time data before le 4.8 5.5 4.8 5.5 ns t su s e t up ti me data before clk 4.9 5.5 4.6 5.5 ns t h hold time data after le 1.8 1.8 1.8 1.8 ns t h h o ld ti me data after clk 1.1 1.1 1.1 1.1 ns 2 these parameters are warranted but not production tested. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 8 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) parameter from to v cc =5v SN54FB1651 sn74fb1651 unit parameter from (input) to (output) v cc = 5 v , t a = 25 c SN54FB1651 t a = 0 c to 70 c t a = 40 c to 85 c unit min typ max min max min max min 2 max 2 f max 150 150 150 150 mhz t plh ai b 1.8 3.7 5.3 1.8 6.6 1.8 6.2 1.8 6.3 ns t phl ai b 2.9 4.4 6 2.9 7.3 2.9 6.6 2.9 7.2 ns t plh leab b 2.7 4.2 5.8 2.7 6.9 2.7 6.4 2.7 6.5 ns t phl leab b 3.5 5 6.5 3.5 7.5 3.5 7.3 3.5 7.3 ns t plh clkab b 2.3 3.9 5.5 2.3 6.5 2.3 6 2.3 6.1 ns t phl clkab b 2.9 4.5 6.1 2.9 6.8 2.9 6.7 2.9 6.7 ns t plh 2clkab 2clkab 4.6 6.9 8.8 4.6 10.7 4.6 9.9 4.6 10.2 ns t phl 2clkab 2clkab 4.9 6.5 8.1 4.9 9.2 4.9 8.8 4.9 8.9 ns t plh b ao 3.5 5.9 7.9 3.5 9.7 3.5 8 3.5 8.9 ns t phl b ao 2.2 3.7 5.3 2.2 6 2.2 5.7 2.2 5.8 ns t plh leba ao 1.8 3.2 4.6 1.8 5.4 1.8 5.1 1.8 5.2 ns t phl leba ao 1.7 3 4.4 1.7 5.1 1.7 4.7 1.7 4.8 ns t plh clkba ao 1.8 3.1 4.6 1.8 5.4 1.8 5.1 1.8 5.1 ns t phl clkba ao 1.7 3.1 4.6 1.7 5.3 1.7 4.9 1.7 5 ns t plh 2clkab 2clk 6.4 9.7 11.8 6.4 15 6.4 13.4 6.4 13.8 ns t phl 2clkab 2clk 4.1 6.9 8.9 4.1 11.2 4.1 10.3 4.1 10.5 ns t plh oeb b 2.7 4.6 6.4 2.7 7.4 2.7 6.7 2.7 7 ns t phl o eb b 2.9 4.1 5.9 2.9 6.8 2.9 6.6 2.9 6.6 ns t plh oeb b 2.6 4.3 6.2 2.6 7.2 2.6 6.6 2.6 6.7 ns t phl oeb b 3.4 4.6 6.4 3.4 7.2 3.4 7 3.4 7 ns t pzh oea ao 1.4 2.9 4.4 1.4 5.3 1.4 4.9 1.4 5 ns t pzl o ea ao 1.4 2.6 4 1.4 4.9 1.4 4.6 1.4 4.7 ns t phz oea ao 1.7 3.4 5.1 1.7 5.9 1.7 5.8 1.7 5.8 ns t plz o ea ao 2.2 3.6 5 2.2 5.8 2.2 5.5 2.2 5.6 ns t pzh oea ao 1.7 3.3 4.7 1.7 5.9 1.7 5.5 1.7 5.6 ns t pzl oea ao 1.7 3.1 4.4 1.7 5.4 1.7 5.1 1.7 5.2 ns t phz oea ao 1.5 2.9 4.5 1.5 5.2 1.5 5.1 1.5 5.1 ns t plz oea ao 2 3.1 4.6 2 5 2 4.8 2 4.8 ns t t 2 b outputs (1.3 v to 1.8 v) 0.9 1.7 0.3 6.8 0.5 4.6 0.5 4.6 ns t t transition time 2 ao outputs (10% to 90%) 0.5 2 0.3 4.3 0.4 4.2 0.4 4.2 ns b -port input pulse rejection 2 1 1 1 1 ns 2 these parameters are warranted but not production tested. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 9 post office box 655303 ? dallas, texas 75265 output skew characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter v cc = 5 v, t a = 25 c SN54FB1651 sn74fb1651 unit parameter min typ max 2 min max 2 min max 2 unit t sk (p) 3 skew between drivers switching in any direction in the same package clk to b and 2clkab 4 ns t sk(p) i n any di rect i on i n t h e same pac k age clk to b 1.5 ns t sk(p) skew for any single channel |t phl t plh | ai to b or b to ao 1 ns t sk(o) skew between drivers in the same package ai to b or b to ao 0.5 ns 2 these parameters are warranted but not production tested. 3 skew values are applicable for clk mode only. skew values are applicable for through mode only. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
SN54FB1651, sn74fb1651 17-bit ttl/btl universal storage transceivers with buffered clock lines scbs177i october 1993 revised june 1997 10 post office box 655303 ? dallas, texas 75265 parameter measurement information from output under test c l = 50 pf (see note a) load circuit for a outputs s1 500 w 500 w from output under test load circuit for b outputs 2.1 v 16.5 w c l = 30 pf (see note a) test point t h t su t phl t plh output 3 v 0 v v oh v ol data input timing input 3 v 0 v 0 v t phl t plh 2 v 1 v v oh v ol voltage waveforms propagation delay times (b to a) voltage waveforms propagation delay times (a to b) voltage waveforms setup and hold times output control output waveform 1 s1 at 7 v (see note b) output waveform 2 s1 at open (see note b) v ol v oh t plz t pzh t pzl t phz 3.5 v 0 v v ol + 0.3 v v oh 0.3 v 0 v 3 v t w voltage waveforms pulse duration voltage waveforms enable and disable times (a port) t plh /t phl t plz /t pzl t phz /t pzh open 7 v open test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: ttl inputs: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns; btl inputs: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. 7 v open 1.5 v 1.5 v 1.5 v 3 v 0 v 1.5 v 1.5 v input input 1.5 v 1.5 v 1.55 v 1.55 v output input 1.5 v 1.5 v 1.55 v 1.55 v 1.5 v 1.5 v 1.5 v 1.5 v 3 v gnd figure 1. load circuits and voltage waveforms
important notice texas instruments (ti) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. ti warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the risk of the customer. use of ti products in such applications requires the written approval of an appropriate ti officer. questions concerning potential risk applications should be directed to ti through a local sc sales office. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does ti warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. copyright ? 1996, texas instruments incorporated

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